The present invention relates to semiconductor structures, and more particularly to junction on insulator (JOI) structures which have low junction leakage, reduced junction capacitance, and substantially little or no floating body effects which, if present, may degrade the stability and/or threshold voltage of the semiconductor device. The present invention also provides a JOI structure which, not only eliminates isolation regions between adjacent source/drain diffusion regions of opposite dopant polarity, but the need for employing a local interconnect wiring region for connecting the source/drain diffusion regions of opposite dopant polarity to each other.
A significant fraction of the total power consumption in low-power bulk complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) and other devices is attributed to the junction leakage in the array which occurs during standby, i.e., when the device is not actively in operation. In typical low-power applications, the active duty factor is less than 1%. This results injunction leakage during standby contributing significantly to the total power. It is therefore necessary to find a means of reducing junction leakage in low-power bulk CMOS SRAMs.
Another problem facing many bulk semiconductor devices is performance degradation which is caused by high source/drain junction capacitance. Reduction in source/drain junction capacitance is thus required in many applications for improved performance.
It is known in the semiconductor industry that a junction on insulator structure allows for both source/drain junction leakage and capacitance to be reduced. Most of the commonly available junction on insulator structures are formed using a silicon-on-insulator (SOI) which includes a buried oxide layer that electrically isolates a top Si-containing layer from a bottom Si-containing substrate layer. A major drawback in forming junction on insulator structures on an SOI is that costly processing steps are required, particularly for the fabrication of the SOI substrate material itself. Moreover, SOI materials are highly susceptible to floating body effects which greatly limit the stability and threshold voltage of the overall device. Another drawback of using SOI materials in forming JOI structures is that it is extremely difficult and, in some instances, nearly impossible to integrate a bulk semiconductor device with a structure containing an SOI material. Such bulk semiconductor devices may include vertical bipolar transistors which may require an SOI material that is considerably thicker than desired for SOI MOSFETs.
A further problem facing bulk semiconductor devices is the need to have source/drain diffusion regions separated by an isolation region. The isolation region prevents the N+ diffusion from shorting to the adjacent N-well/substrate and the P+ diffusion from shorting to the adjacent P-well/substrate. A typical prior art SRAM cell layout is shown in FIGS. 1A (top-view) and 1B (cross-section through X1-X1xe2x80x2). Specifically, the prior art structure shown in FIGS. 1A-1B comprises semiconductor substrate 10 having P-well region 12 and N-well region 14 formed therein. The structure also includes isolation regions 16 that are formed in semiconductor substrate 10 which separate source/drain regions 38 of opposite dopant polarity, i.e., P+ and N+, from each other. The prior art structure also includes at least one patterned gate stack region 18 formed atop a surface of semiconductor substrate 10. The at least one patterned gate stack region includes at least gate dielectric 24, gate conductor 26 and sidewall spacers 30.
The prior art structure of FIGS. 1A-1B also includes local interconnect wiring level 75 formed atop source/drain diffusion regions 38 of opposite dopant polarity and cross-connect 77 formed atop a portion of interconnect wiring level 75. Note that the presence of the isolation region between adjacent source/drain diffusion regions of opposite dopant polarity shown in FIG. 1 results in a cell layout that is not compact.
In the cell layout of FIG. 1A, BL denotes the bitlines of the cell, BL* denotes bitline complement, and WL denotes the wordlines of the cell, which lay orthogonal to the bitlines. Vdd represents power supply, and GND represents ground.
Yet another problem associated with the prior art FIGS. 1A and 1B is the need for local interconnect wiring level 75 which is employed therein for connecting source/drain diffusion regions 38 of opposite dopant polarity that are separated by isolation regions 16. Thus, the local interconnect wiring level shown in these prior art figures is not free to be used with other wiring levels.
In view of the above drawbacks in the prior art, there is still a need for developing a new and improved JOI structures on a surface of a bulk semiconductor substrate which have low junction leakage and reduced junction capacitance associated therewith. Additionally, there exists a need for providing a JOI structure which, not only eliminates the isolation regions between source/drain diffusion regions of opposite dopant polarity, but the need for using a local interconnect wiring level as a means for connecting adjacent source/drain diffusion regions of opposite dopant polarity to each other.
One object of the present invention is to provide JOI structures on a bulk semiconductor substrate.
A further object of the present invention is to provide JOI structures in which standby power reduction caused by junction leakage is substantially reduced.
A yet further object of the present invention is to provide JOI structures having reduced junction capacitance.
A still further object of the present invention is to provide JOI structures which exhibit little or substantially no floating body effects.
An even further object of the present invention is to provide JOI structures which eliminate the need of using an isolation region to physically separate source/drain diffusion regions of opposite dopant polarity from each other.
An yet further object of the present invention is to provide JOI structures which eliminate the local interconnect wiring level which is employed in prior art structures for electrically connecting source/drain diffusion regions of opposite dopant polarity to each other.
Another object of the present invention is to provide JOI structures which result in a compact, dense cell layouts, e.g., SRAMs or inverters.
These and other objects and advantages are achieved in the present invention by providing JOI structures which contain an insulating layer such as an oxide formed beneath a conductive region, e.g., source/drain diffusion regions, but not under the channel region of a patterned gate stack region.
In one embodiment of the present invention, the inventive JOI structure comprises: at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate having source/drain diffusion regions of opposite dopant polarity abutting each other present therein, said source/drain diffusion regions are present atop an insulating layer, said insulating layer not being present beneath said at least one patterned gate stack region.
Note in the embodiment mentioned above, no isolation regions separate the source/drain regions of opposite dopant polarity. The inventive JOI structure mentioned above may also include a salicide region present atop the source/drain diffusion regions of opposite dopant polarity. In such an embodiment, a cross-connect layer may be formed on a portion of said salicide layer.
Another JOI structure that is disclosed in the present application comprises:
at least one patterned gate stack region present atop a semiconductor substrate, said semiconductor substrate containing at least a conductive region other than source/drain diffusion regions present atop an insulating layer embedded therein, said insulating layer not being present beneath said at least one patterned gate stack region, wherein said conductive region is in contact with vertical sidewalls of source/drain extension regions present in said semiconductor substrate, beneath said at least one patterned gate stack region.
In such an embodiment, a cross-connection layer may be formed atop the conductive layer.
A yet other JOI structure that is provided herein comprises:
at least one patterned gate stack region present atop a semiconductor substrate, said at least one patterned gate stack region having small, controlled dimension regions of conductive material adjacent thereto, each of which is in contact with said semiconductor substrate and self-aligned to an adjacent gate edge.